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Study on Simulation and Profile Prediction of Atomic Layer Deposition
Authors: Lei Qu, Chen Li, Jiang Yan et al.
Institution:North China University of Technology
Keywords:Atomic Layer Deposition;process simulation;profile model;temperature fitting;film of HfO2
doi:10.33079/jomm.20030303
Issue 3: 20030303, 2020 | PDF
Research Article
Published: Oct. 8, 2020
Views:195
Abstract: The Atomic Layer Deposition process (ALD) is widely used in FinFET, 3D-NAND and other important technologies because of its self-limiting signature and low growth temperature. In recent years, the ...
Study of Inverse Lithography Approaches based on Deep Learning
Authors: Xianqiang Zheng, Xu Ma, Shengen Zhang et al.
Institution:Key Laboratory of Photoelectronic Imaging Technology and System of Ministry of Education of China, School of Optics and Photonics, Beijing Institute of Technology, China
Keywords:Computational lithography;inverse lithography technology (ILT);optical proximity correction (OPC);deep learning
doi:10.33079/jomm.20030301
Issue 3: 20030301, 2020 | PDF
Research Article
Published: Oct. 7, 2020
Views:281
Abstract: Computational lithography (CL) has become an indispensable technology to improve imaging resolution and fidelity of deep sub-wavelength lithography. The state-of-the-art CL approaches are capable o...
Recognition and Visualization of Lithography Defects based on Transfer Learning
Authors: Bo Liu, Pengzheng Gao, Libin Zhang et al.
Institution:School of Information, North China University of Technology, Beijing
Keywords:transfer learning;neural network;lithography defects;visualize;Grad-CAM
doi:10.33079/jomm.20030302
Issue 3: 20030302, 2020 | PDF
Research Article
Published: Oct. 5, 2020
Views:240
Abstract: Yield control in the integrated circuit manufacturing process is very important, and defects are one of the main factors affecting chip yield. As the process control becomes more and more critical ...
Issue 2: 20030203, 2020 | PDF
Research Article
Published: June 29, 2020
Views:1179
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...
Current Status of the Integrated Circuit Industry in China ― Overview of Semiconductor Materials Industry
Authors: Litho World
Keywords:IC Industry;Material lndustry
doi:10.33079/jomm.20030106
Issue 1: 20030106, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1376
Abstract: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momen...
A Device Design for 5 nm Logic FinFET Technology
Authors: Yu Ding, Yongfeng Cao, Xin Luo et al.
Institution:Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai
Keywords:5nm FinFET;brief process flow;key dimensions;simulated device DC/AC performance;RO PPA performance
doi:10.33079/jomm.20030105
Issue 1: 20030105, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1212
Abstract: With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, N...
A Study of 2D Assist Feature Placement
Authors: Liang Zhu, Barry Ma, Lin Shen et al.
Institution:Synopsys Inc., 1027 ChangNing Road, Shanghai, China, 200050
Keywords:Assist Feature;Inverse Lithography Technology;Low K1 Lithography;Machine Learning
doi:10.33079/jomm.20030104
Issue 1: 20030104, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1374
Abstract: Sub-resolution assist features have been widely recognized in lithography patterning. In general, the insertion of assist features in optically adjacent space around main designed features, will ch...
Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography
Authors: Yushu Yang, Yanli Li, Qiang Wu et al.
Institution:Shanghai IC R&D Center, 497, Gaosi Road, Zhangjiang Hi, -, Tech Park, Shanghai
Keywords:5 nm Logic Process;EUV;metal gate cut;SAC;BAC;self-aligned LELE
doi:10.33079/jomm.20030103
Issue 1: 20030103, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1606
Abstract: 5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries. In a typical 5 nm logic process, the Fin pitch is 22~27 nm, the contact-poly pi...
Metrology Challenges in 3D NAND Flash Technical Development and Manufacturing
Authors: Wei Zhang, Jun Xu, Sicong Wang et al.
Institution:Yangtze Memory Technologies Co., Ltd., Wuhan
Keywords:3D NAND;Metrology;Semiconductor;HAR;Process Control
doi:10.33079/jomm.20030102
Issue 1: 20030102, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1601
Abstract: 3D NAND technical development and manufacturing face many challenges to scale down their devices, and metrology stands out as much more difficult at each turn. Unlike planar NAND, 3D NAND has a thr...
DFM: “Design for Manufacturing” or “Design Friendly Manufacturing”
Authors: Wenzhan Zhou, Hung-Wen Chao, Yu Zhang et al.
Institution:Shanghai Huali Integrated Circuit Corp, China
Keywords:Design for Manufacturing (DFM);Design Friendly Manufacturing;EUV Lithography;Source Mask Optimization (SMO);Design Technology Co-optimization (DTCO);Process Window;Process Variation
doi:10.33079/jomm.20030101
Issue 1: 20030101, 2020 | PDF
Research Article
Published: March 30, 2020
Views:1373
Abstract: As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc.) pro...